The present technique relates to an interconnect and to a method of operation of such an interconnect.
An interconnect can be used to connect a plurality of master devices with a plurality of slave devices in order to allow transactions to take place between those master devices and those slave devices. In some interconnects, there is a requirement for Ordered Write Observation (OWO) behaviour to be observed at the interface of the interconnect with at least one of the master devices. In respect of such an interface to a master device, OWO behaviour requires that if the master device is able to observe the results of a write transaction with a particular transaction identifier, it will also necessarily be able to observe the results of all other write transactions having the same transaction identifier that were issued before that write transaction.
Separate to the issue of maintaining OWO behaviour at one or more interfaces to the master devices, it is also known that interconnects typically need to incorporate deadlock avoidance circuits to ensure that transactions are processed through the interconnect in a way that will not give rise to deadlock situations occurring. As an example, it is known to monitor write response signals returned through the interconnect from the slave devices, and to use that write response information to determine when it is safe to allow new transactions to be issued through the interconnect. In known systems, the use of such deadlock avoidance schemes can also have the by-product of ensuring that the earlier mentioned OWO behaviour is observed.
However, deadlock avoidance circuitry reduces potential performance by increasing latency of write transactions, and may also be complex and costly to implement, and in some interconnects other structures can be incorporated to alleviate the potential for certain deadlock conditions. For example, it is known to provide write response re-order buffers to enable the order in which write response signals are returned to a master device to be re-ordered relative to the order in which they are received by the interconnect. This has the potential to significantly reduce the latency impact by reducing the extent to which the deadlock avoidance circuitry is required within the interconnect. However, it is still necessary to ensure any required OWO behaviour is observed, and this limits the potential reductions in latency when the deadlock avoidance circuitry is used to ensure OWO behaviour.